By Dongwoo Hong
With the expanding call for for larger information bandwidth, conversation structures’ information premiums have reached the multi-gigahertz diversity or even past. Advances in semiconductor applied sciences have speeded up the adoption of high-speed serial interfaces, corresponding to PCI-Express, Serial-ATA, and XAUI, with the intention to mitigate the excessive pin-count and the data-channel skewing difficulties. besides the fact that, with the expanding variety of I/O pins and bigger info charges, major demanding situations come up for checking out high-speed interfaces by way of try out price and caliber, specially in excessive quantity production (HVM) environments. Efficient try out Methodologies for High-Speed Serial hyperlinks describes intimately a number of new and promising suggestions for cost-effectively checking out high-speed interfaces with a excessive try out insurance. One basic concentration of Efficient attempt Methodologies for High-Speed Serial hyperlinks is on effective trying out equipment for jitter and bit-error-rate (BER), that are well-known for quantifying the standard of a verbal exchange approach. quite a few research in addition to experimental effects are offered to illustrate the validity of the offered techniques.
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Extra resources for Efficient Test Methodologies for High-Speed Serial Links
T/ and an RJ component n(t) with an rms value of ¢RJ . Errors occur when the input jitter exceeds the error boundaries, which are the recovered clock jitter plus or minus T/2. Because the CDR circuit can completely track the PJ, the recovered clock jitter will be the same as s(t). ¨t/ T=2: The left hand sides represent the total input jitter, and the right hand sides represent the error boundaries. 10) 2. Region 2 Since the phase response of the CDR circuit has a non-zero slope, the PJ in this region is tracked by the CDR circuit with certain delay introduced into the recovered clock.
32 3 BER Estimation for Linear Clock and Data Recovery Circuit For PRBS Pattern For the PRBS pattern, the equations derived for Aeff and ¢eff in each region do not change. The only differences are: (1) The time delay (t0 ) and the magnitude of the recovered clock jitter in Region 3 (a2 ) will be calculated using Eq. 6 instead of Eq. 4. (2) The transition density (¡T ) is 1/2. 3 BER Analysis Including Intrinsic Noise in the CDR Circuit The jitter transfer analysis can be extended to consider the intrinsic noise of the CDR circuit.
Therefore, only the RJ contributes to the BER. ¨t/ and an RJ component n(t) with an rms value of ¢RJ . Errors occur when the input jitter exceeds the error boundaries, which are the recovered clock jitter plus or minus T/2. Because the CDR circuit can completely track the PJ, the recovered clock jitter will be the same as s(t). ¨t/ T=2: The left hand sides represent the total input jitter, and the right hand sides represent the error boundaries. 10) 2. Region 2 Since the phase response of the CDR circuit has a non-zero slope, the PJ in this region is tracked by the CDR circuit with certain delay introduced into the recovered clock.